1. Field of the Invention
The present invention relates generally to producing a reference frequency signal for a phase locked loop (PLL), and more particularly to methods and apparatus for producing a reference frequency signal for a PLL with use of a reference frequency quadrupler.
2. Description of the Related Art
A conventional phase locked loop (PLL) typically includes a frequency phase detector which receives a reference signal, a filter, a voltage-controlled oscillator (VCO), and a divider circuit. If the reference signal received by the frequency phase detector has a relatively low frequency, a large feedback divider ratio is required by the PLL. A large feedback divider ratio requires that the divider circuit have a relatively large number of dividers, which undesirably introduces phase xe2x80x9cjitterxe2x80x9d into the signals. The large feedback divider ratio also means that the loop gain of the PLL will be lower for a given supply voltage, which makes the gain distribution for noise less ideal and also increases jitter.
One solution to this problem is to increase the frequency of the reference signal received by the frequency phase detector. However, conventional XOR-based frequency doublers typically distort the duty cycle of reference signals due to integrated circuit (IC) process variations. This distortion may be severe enough to render the approach ineffective.
According to the present invention, circuitry for a phase locked loop (PLL) includes a first frequency doubler; a first equalizer having an input coupled to an output of the first frequency doubler; a second frequency doubler having an input coupled to an output of the first equalizer; and a second equalizer having an input coupled to an output of the second frequency doubler and an output which is fed into the PLL. Each one of the frequency doublers includes a delay circuit having an input coupled to the input of the frequency doubler; and an XOR circuit having a first input coupled to an output of the delay circuit and a second input coupled to the input of the frequency doubler.
The combination of the two frequency doublers in series quadruples the reference signal into the PLL. The first equalizer helps restore the duty cycle of the signal before it enters the second frequency doubler, and the second equalizer helps restore the duty cycle before the signal enters the PLL. The increased (quadrupled) reference frequency allows the PLL to have a smaller feedback divider ratio and therefore fewer dividers; fewer dividers result in less circuitry in the PLL feedback path which reduces jitter. A reduced divider ratio also allows a higher loop gain for a given supply voltage, which produces a more ideal gain distribution for noise and reduces jitter as well. Importantly as well, controls for the selection of the initial reference signal are advantageously provided.